ASIC Verification Engineer
Workplace: Lund, Sverige
Expires: August 24, 2025
Join the ASIC verification team at Axis Communications AB to work with verifying core hardware IPs and subsystems for the company's ARTPEC chips. This senior engineering role involves using advanced verification techniques including Coverage-driven Constrained Random Verification with SystemVerilog and UVM, and programming in Python and other languages. The role offers opportunities for continuous learning, collaboration in an agile environment, and contributing to world-class product development in a global tech company.
Main requirements:
- Experience in ASIC verification or a relevant engineering degree.
- Proficiency in Coverage-driven Constrained Random Verification using SystemVerilog and UVM.
- Strong programming skills, especially in Python.
- Ability to work collaboratively in a team environment.
- Willingness to continuously learn and apply new verification technologies.
Responsibilities:
- Verify in-house developed hardware IPs and subsystems for ARTPEC chips using simulation and formal methods.
- Develop and maintain complex verification environments using object-oriented frameworks.
- Debug and identify potential issues in hardware designs.
- Investigate and evaluate new verification technologies and tools.
- Share knowledge and collaborate within the team.
- Possibility to write papers and present at international conferences.
Required hard skills:
- SystemVerilog
- UVM (Universal Verification Methodology)
- Coverage-driven Constrained Random Verification
- Python programming
- Hardware debugging
- Object-oriented programming concepts
Recommended hard skills:
- Formal verification techniques (e.g., connectivity checking, formal property verification)
- Programming in C, C++, or SystemC
- Transaction Level Modeling (TLM)
- Clock-domain crossing verification
Soft skills:
- Collaboration and teamwork
- Knowledge sharing
- Problem-solving
- Creativity
- Continuous learning mindset
- Communication skills
Coding languages:
- SystemVerilog
- Python
- C
- C++
- SystemC
Frameworks:
- UVM (Universal Verification Methodology)
- Object-oriented verification frameworks
Operating systems:
- Not explicitly specified
Natural languages:
- English (Proficient)
Cultural skills:
- Agile working methods
- Sustainability awareness
- Equality and inclusion
Apply for this job
You might also like:
- Pega Lead Architect (CLSA)
- Dispatch & Access Coordinator
- Senior IT Requirements Analyst
- Experienced Network Technician
- IAM Service Manager
- HMI Engineer for Control Systems in HVDC Upgrade Project
- System Administrator
- Senior Data Engineer with Snowflake Experience
- Investigator PSA within Systems Engineering
- WAN Network Engineer