Verification Engineer
Workplace: Linköping, Sverige
Expires: November 19, 2025
We are looking for an experienced ASIC Verification Engineer with knowledge in UVM methodology to join our team developing next-generation device architectures. This role focuses on ensuring high-quality, robust designs through well-structured and thorough verification processes.
Main requirements:
  • 5+ years of hands-on experience in ASIC verification, focusing on UVM and System Verilog.
  • Master's degree in Electrical or Computer Engineering or equivalent.
  • Solid understanding of formal verification techniques.
  • Good debugging and problem-solving skills.
  • Effective communicator able to work independently and collaboratively.
Responsibilities:
  • Define and execute verification strategies and plans based on functional specifications.
  • Develop and maintain UVM-based verification environments and testbenches.
  • Analyze and drive closure of functional and code coverage metrics.
  • Debug RTL in close collaboration with design engineers.
  • Contribute to the improvement of verification methodologies, tools, and processes.
Required hard skills:
  • ASIC verification
  • UVM methodology
  • System Verilog
  • Formal verification techniques
  • RTL debugging
Recommended hard skills:
  • C programming language
  • Emulation
  • High-Level Synthesis (HLS)
Soft skills:
  • Effective communication
  • Problem-solving
  • Ability to work independently
  • Team collaboration
Coding languages:
  • System Verilog
  • C
Frameworks:
  • UVM
Natural languages:
  • English (Proficient)
Cultural skills:
  • Innovation-driven mindset
  • Collaboration
  • Supportive and fun workplace culture
  • Diversity and inclusion
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