Senior FPGA Developer
Workplace: Sverige
Expires: August 20, 2025
A senior role focused on FPGA and ASIC design, implementation, and verification within an agile team environment, requiring strong technical expertise and collaboration skills.
Main requirements:
- Proven RTL design and verification experience for FPGA/ASIC
- Strong proficiency in SystemVerilog or VHDL
- Hands-on synthesis and implementation skills
- Background in IP design and development
- Familiarity with UVM-based verification methodologies
- Experience in top-level integration and debugging
- Understanding of CI/CD practices in agile teams
- Proficiency with version control tools, especially Git
- Experience with scripting languages such as TCL, Python, Perl, Cshell, or Bash
- Strong interpersonal and communication skills
- Swedish citizenship due to security clearance and background checks
Responsibilities:
- Perform synthesis and implementation for FPGA and ASIC designs
- Design and verify RTL using SystemVerilog or VHDL
- Develop and integrate IP blocks into larger systems
- Contribute to top-level integration and system-level validation
- Collaborate within agile teams supporting continuous integration and delivery workflows
- Apply scripting to automate design and verification tasks
- Communicate effectively with cross-functional teams
Required hard skills:
- RTL design and verification
- SystemVerilog
- VHDL
- FPGA/ASIC synthesis and implementation
- IP design and development
- UVM verification methodology
- CI/CD processes
- Git version control
- Scripting (TCL, Python, Perl, Cshell, Bash)
Soft skills:
- Strong interpersonal skills
- Effective communication
- Collaboration and teamwork
Coding languages:
- SystemVerilog
- VHDL
- Python
- TCL
- Perl
- Cshell
- Bash
Frameworks:
- UVM
Natural languages:
- English (Proficient)
- Swedish (Working knowledge)
Cultural skills:
- Agile teamwork
- Collaborative communication
- Security compliance and adherence to background check policies